1. Field of the Invention
The present invention relates to a solid-state imaging device having a pixel region, a peripheral circuit region and a scribe lane region on the same semiconductor chip and a method for fabricating the same. More particularly, the present invention relates to a solid-state imaging device in which dummy patterns are provided in a peripheral circuit region and a scribe lane region and a method for fabricating the same.
2. Description of the Background Art
In the field of semiconductor integrated circuits, while a microfabrication of the semiconductor integrated circuit progresses, advancements have also been made to develop a device having a special function such as a solid-state imaging device. For example, in a solid-state imaging device called as a CMOS image sensor, an integrated circuit different from a commonly used integrated circuit is provided. On a main surface of a semiconductor substrate, such an integrated circuit different from the commonly used one has a pixel region, a peripheral circuit region which is provided around the periphery of the pixel region and composed of various logic circuits such as a pixel scanning circuit and a pixel signal processing circuit, and a scribe lane region which is provided around the periphery of the peripheral circuit region. These regions are integrally formed on one semiconductor chip, that is, on the same semiconductor chip. In recent years, in such a solid-state imaging device, as a size of a semiconductor chip is reduced and the number of pixels used in the solid-state imaging device is increased, a wiring portion, in particular, has been microfabricated accordingly. For microfabricating the commonly used integrated circuit and solid-state imaging device, a technology for planarizing a surface of an interlayer insulation film such as a CMP (Chemical Mechanical Polishing) is utilized.
In the solid-state imaging device, a gate electrode of an electrical charge reading transistor is provided on a silicon substrate, and an interlayer insulation film is provided over the entirety of a chip so as to cover the gate electrode therewith. A surface of the interlayer insulation film needs to be formed flat. Conventionally, in order to form the flat surface, the CMP is adopted to reduce a local level difference on a surface of each fine pattern. However, a problem still lies in a level difference on the surface of the interlayer insulation film covering the entirety of the chip (i.e., a global level difference). The global level difference is a level difference, on the surface of the interlayer insulation film, existing from a center portion to peripheral portion of the chip when viewed from the perspective of the entirety of the chip as a whole.
FIG. 8 is a diagram illustrating an exemplary global level difference of a conventional solid-state imaging device. In FIG. 8(a), the pixel region, the peripheral circuit region located around the periphery of the pixel region and the scribe lane region located around periphery of the peripheral circuit region are disposed on the surface of the chip. FIGS. 8(b) and (c) are cross-sectional views along lines Xa-Xb and Ya-Yb of FIG. 8(a), respectively, each of which illustrating a measurement result of a height distribution of a surface of a BPSG (Boron Phosphorous Silicate Glass) film after the CMP is performed on the surface thereof. The BPSG film is an interlayer insulation film (a contact layer). This measurement result shows that a height of the surface of the BPSG film is the greatest at the center portion of the chip (i.e., a center portion of the pixel region), and is the lowest at the peripheral portion of the chip (i.e., a peripheral portion of the scribe lane region).
The global level difference is generated since a polishing rate of the BPSG film is different among the three regions. Specifically, the polishing rate of the BPSG film is high in the peripheral circuit region and the scribe lane region, and low in the pixel region. During the CMP, these three regions are simultaneously polished by means of a single polishing pad. Therefore, a high polishing rate in the peripheral circuit region exerts an influence on the polishing rate in the pixel region. Thus, in the pixel region, the polishing rate becomes gradually higher from its center portion to peripheral portion. As a result, as shown in FIG. 8, the height of the surface of the BPSG film included in the pixel region becomes gradually lower from its center portion to peripheral portion after the CMP is performed on the surface thereof.
As described above, the polishing rate of the BPSG film is high in the peripheral circuit region and the scribe lane region, and low in the pixel region. This is because an area in which the interlayer insulation film is to be polished is small in the peripheral circuit region and the scribe lane region, and large in the pixel region. The larger the area in which the interlayer insulation film is to be polished is, the smaller the polishing rate (a polishing speed) tends to become.
Conventionally, the area in which the interlayer insulation film is to be polished is small in the peripheral circuit region and the scribe lane region, and large in the pixel region. The reason therefor will be described below. In the solid-state imaging device comprising the pixel region, the peripheral circuit region and the scribe lane region, all of which are provided on the same semiconductor chip, a pattern density occupied by a gate electrode is higher in the pixel region than in the peripheral circuit region or the scribe lane region.
Furthermore, a photodiode is provided in the pixel region. On the photodiode, an insulation film is provided so as to protect the photodiode from plasma used when a side wall is formed for a pixel driving MOS transistor which is provided in the peripheral circuit region. On the contrary, the plasma exerts little influence on a source region and a drain region of the pixel driving MOS transistor provided in the peripheral circuit region. No MOS transistor is provided in the scribe lane region. Therefore, the insulation film for protecting the source region of the MOS transistor is not necessarily needed in the peripheral circuit region and the scribe lane region. After the insulation film for protecting the photodiode is provided, the interlayer insulation film is provided over the entirety of the chip so as to cover the insulation film therewith. In order to planarize the surface of the interlayer insulation film, the CMP is performed on the surface thereof.
A height of the surface of the interlayer insulation film included in the pixel region, where the insulation film for protecting the photodiode is provided and the pattern density occupied by the gate electrode is high, is greater than that of the interlayer insulation film included in each of other two regions, where no insulation film for protecting the photodiode is provided and the pattern density occupied by the gate electrode is low. Therefore, the pixel region has a larger area of the interlayer insulation film on which the CMP needs to be performed than the other two regions. In this case, the polishing rate in the pixel region becomes higher than that in the peripheral circuit region or the scribe lane region. As described above, the high polishing rate in the peripheral circuit region exerts an influence on the polishing rate in the pixel region. Thus, after the CMP is performed on the surface of the interlayer insulation film, the height of the surface thereof included in the pixel region is the greatest at its center portion, and the lowest at its peripheral portion. In other words, the global level difference is generated in the pixel region. When the global level difference exists in the pixel region, a distance between a photodiode, acting as a photoreceptor for converting an optical signal into an electrical signal, and a condenser microlens, provided above the photodiode with the interlayer insulation film therebetween, becomes larger at its center portion and smaller at its peripheral portion. This may cause a shading phenomenon in which an intensity of light incident to the photodiode is different between the central portion of the pixel region and the peripheral portion thereof.
As described above, when the global level difference is generated in the pixel region, shading is caused. As a result, a sensitivity to incident light and an incident angle characteristic are deteriorated. Thus, it is necessary to reduce the global level difference to a minimum.
A detailed example of the conventional solid-state imaging device in which such a global level difference is generated will be described with reference to the drawings. FIGS. 9 and 10 are diagrams illustrating steps of a method for fabricating the conventional solid-state imaging device. Each of FIGS. 9 and 10 shows cross sections of a pixel region 11a, a peripheral circuit region 11b and a scribe lane region 11c, all of which are provided in the solid-state imaging device. The step shown in FIG. 10(a) is a step subsequent to the step shown in FIG. 9(d).
Hereinafter, the method for fabricating the conventional solid-state imaging device will be described.
Firstly, on a semiconductor substrate in which a photodiode 13 and a STI (Shallow Trench Isolation) 12 are formed, a polysilicon 14 is deposited (FIG. 9(a)). Then, the polysilicon 14 is selectively etched so as to form gate electrodes 14a and 14b of MOS transistors (FIG. 9(b)). In the peripheral circuit region 11b, a low concentration impurity diffusion layer 15 having a LDD (Lightly Doped Drain) structure is formed in order to alleviate an electrical field in the vicinity of a drain region of the MOS transistor (FIG. 9(c)). Over the entirety of the semiconductor substrate, a TEOS (Tetra Ethyl Ortho Silicate) film 16 acting as an insulation film is deposited (FIG. 9(d)). Thereafter, in order to form a side wall spacer 16b made of the TEOS film 16 in the peripheral circuit region 11b, an etchback is performed by a strong anisotropic etching using plasma in the peripheral circuit region 11b (FIG. 10(a)). At this time, in the pixel region 11a, the TEOS film 16a is caused to remain on the photodiode 13 such that the photodiode 13 is not damaged by the plasma. In order to cause the TEOS film 16a to remain on the photodiode 13, a photo resist film which is not shown is formed on the TEOS film 16 corresponding to a position at which the photodiode 13 is located. The photo resist film is removed after forming the side wall spacer 16b. The characteristic of a fabrication process of the solid-state imaging device is that the TEOS film 16a is caused to remain on the photodiode 13.
Next, a high concentration source/drain diffusion layer 17 is formed (FIG. 10(b)). Further, through an opening formed by removing the TEOS film 16 due to the etching, a metal silicide layer 18 is formed on upper portions of the gate electrodes 14a and 14b (FIG. 10(b)). Thereafter, a BPSG film 19 is formed over the entirety of the semiconductor substrate such that the gate electrodes 14a and 14b and the TEOS films 16a and 16b are to be buried thereunder (FIG. 10(c)). Note that in the scribe lane region 11c, neither the gate electrode nor the TEOS film exists. Therefore, the pattern density occupied by the gate electrode is higher in the order of the pixel region 11a, the peripheral circuit region 11b and the scribe lane region 11c. Furthermore, the insulation film 16a for protecting the photodiode 13 remains in the pixel region 11a. Therefore, among the pixel region 11a, the peripheral circuit region 11b and the scribe lane region 11c, the pixel region 11a has the greatest average height of the surface of the BPSG film 19. Thus, among the pixel region 11a, the peripheral circuit region 11b and the scribe lane region 11c, the pixel region 11a also has the largest area in which the BPSG film 19 needs to be polished. However, if the CMP is performed on the surface of the BPSG film 19 in this state, the polishing rate obtained by the CMP is lower in the order of the pixel region 11a, the peripheral circuit region 11b and the scribe lane region 11c. As a result, after the CMP is performed on the surface of the BPSG film 19, a global level difference 110 is generated at boundary portions between the three regions (FIG. 10(d)). For schematically showing the global level difference, in FIG. 10(d), each of the three regions is flat and a level difference exits at the boundary portions between the regions. In practice, however, as shown in FIG. 8, the surface of the BPSG film 19 included in each of the pixel region, the peripheral circuit region and the scribe lane region is slanted, and the height of the surface of the BPSG film 19 becomes gradually lower from the center position of the pixel region to the peripheral portion of the scribe lane region.
As an exemplary technique for planarizing a surface of an insulation film of a solid-state imaging device, there is a technique disclosed in Japanese Laid-Open Patent Publication No. 9-102539 (see FIG. 11). However, this technique is used only for planarizing a surface of a device isolation region 14X formed on a surface of the semiconductor substrate 11X, and is not used for planarizing the surface of the interlayer insulation film.